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ZILOG
Z5380 SCSI
PRODUCT SPECIFICATION
Z5380 SCSI
SMALL COMPUTER SYSTEM INTERFACE (SCSI)
FEATURES
s s s s s
Pin Compatible with the Industry Standard 5380 40-Pin DIP or 44-Pin PLCC Package Styles Low-Power CMOS Asynchronous Interface (Supports 1.5 MB/s) Direct SCSI Bus Interface with On-Board 48 mA Drivers
s s s s s
Supports Target and Initiator Roles Arbitration Support DMA or Programmed I/O Data Transfers Supports Normal or Block Mode DMA Memory or I/O Mapped CPU Interface
GENERAL DESCRIPTION
The Z5380 SCSI (Small Computer System Interface) controller is designed to implement the SCSI protocol as defined by the ANSI X3.131-1986 standard, and is fully compatible with the industry standard 5380. It is capable of operating both as a Target and as an Initiator. Special high-current open-drain outputs enable the Z5380 to directly interface to, and drive, the SCSI bus. The Z5380 has the necessary interface hook-ups which allows the system CPU to communicate with it like any other peripheral device. The CPU can read from, or write to, the SCSI registers which are addressed as standard or memorymapped I/Os (Figure 1). The Z5380 increases the system performance by minimizing the CPU intervention in DMA operations which the SCSI controls. The CPU is interrupted by the SCSI when it detects a bus condition that requires attention. It also supports arbitration and reselection. The Z5380 has the proper hand-shake signals to support normal and block mode DMA operations with most DMA controllers available (Figure 2).
Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below:
Connection
Power Ground
Circuit
VCC GND
Device
VDD VSS
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Z5380 SCSI
GENERAL DESCRIPTION (Continued)
/DB7-/DB0, /DBP
/ACK
/ATN
/BSY
/MSG
I//O
C//D
/REQ
/RST
/SEL
48 mA SCSI Transceivers
/IOR /IOW /CS /RESET A2-A0 D7-D0 CPU BUS Interface
Interface Control Logic
Data Input Register
Data Output Register
DMA Logic
Interrupt Logic
Control Registers
/EOP
READY
DRQ
/DACK
Figure 1. Z5380 Block Diagram
D7-D0 A2-A0 /IOR /IOW /CS /RESET /DACK /EOP DRQ READY IRQ GND
IRQ
/DB7-DB0, /DBP /ACK /ATN /BSY /MSG
Z5380
I//O C//D /REQ /RST /SEL
VDD
Figure 2. Logic Symbol
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/DB4 /DB5 /DB6 /DB7 N/C
Z5380 SCSI
D0
D1
D2
D3
D4
D0 /DB7 /DB6 /DB5 /DB4 /DB3 /DB2 /DB1 /DB0 /DBP GND /SEL /BSY /ACK /ATN /RST I//O C//D /MSG /REQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
D1 D2 D3 D4 D5 D6 D7 A2 A1 VDD A0 /IOW /RESET /EOP /DACK
/DB3 /DB2 /DB1 /DB0 /DBP GND GND /SEL /BSY /ACK /ATN 7 8 9 10 11 12 13 14 15 16
6
5
4
3
2
1 44 43 42 41 40 39 38 37 36 D6 D7 A2 A1 VDD N/C A0 /IOW /RESET /EOP /DACK
D5
Z5380
35 34 33 32 31 30
Z5380
31 30 29 28 27 26 25 24 23 22 21
17 29 18 19 20 21 22 23 24 25 26 27 28
/CS /REQ /RST /MSG DRQ /IOR I//O C//D IRQ N/C RDY
READY /IOR IRQ DRQ /CS
Figure 3b. 44-Pin PLCC Pin Configuration
Figure 3a. 40-Pin DIP Pin Configuration
PIN DESCRIPTION Microprocessor Bus
Figure 3 shows the pins and their respective functions for both the DIP and PLCC. A2-A0 Address Lines (Input). Address lines are used with /CS, /IOR, or /IOW to address all internal registers. /CS Chip Select (Input, Active Low). This signal, in conjunction with /IOR or /IOW, enables the internal register selected by A2-A0, to be read from or written to. /DACK DMA Acknowledge (Input, Active Low). /DACK resets DRQ and selects the data register for input or output data transfers. /DACK is used by DMA controller instead of /CS. DRQ DMA Request (Output, Active High). DRQ indicates that the data register is ready to be read or written. DRQ is asserted only if DMA mode is set in the Command Register. DRQ is cleared by /DACK. D7-D0 Data Lines (Bi-directional, three-state, Active High). Bi-directional microprocessor data bus lines. D0 is the Least Significant Bit of the bus. Data bus lines carry data and commands to and from the SCSI. /EOP End of Process (Input, Active Low). /EOP is used to terminate a DMA transfer. If asserted during a DMA cycle, the current byte will be transferred, but no additional bytes will be requested. /IOR I/O Read (Input, Active Low). /IOR is used in conjunction with /CS and A2-A0 to read an internal register. It also selects the Input Data Register when used with /DACK. /IOW I/O Write (Input, Active Low). /IOW is used in conjunction with /CS and A2-A0 to write an internal register. It also selects the Output Data Register when used with /DACK.
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Z5380 SCSI
PIN DESCRIPTION (Continued)
IRQ Interrupt Request (Output, Active High). IRQ alerts a microprocessor of an error condition or an event completion. READY Ready (Output, Active High). Ready is used to control the speed of Block Mode DMA transfers. This signal goes active to indicate the chip is ready to send/ receive data and remains Low after a transfer until the last byte is sent or until the DMA Mode bit is reset. /RESET Reset (Input, Active Low). /RESET clears all registers. It has no effect upon the SCSI /RST signal. /DB7-/DB0, /DBP Data Bus Bits, Data Bus Parity Bit (Bidirectional, Open-drain). These eight data bits (/DB7-/ DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the most significant bit (MSB) and has the highest priority during the Arbitration phase. Data parity is odd. Parity is always generated and optionally checked. Parity is not valid during Arbitration. I//O Input/Output (Bi-directional, Open-drain). I/O is a signal driven by a Target which controls the direction of data movement on the SCSI bus. True indicates input to the Initiator. This signal is also used to distinguish between Selection and Reselection phases. /MSG Message (Bi-directional, Open-drain, Active Low). This signal is driven by the Target during the Message phase. This signal is received by the Initiator. /REQ Request (Bi-directional, Open-drain, Active Low). Driven by the Target and received by the Initiator, this signal indicates a request for a /REQ//ACK data-transfer handshake. /RST SCSI Bus Reset (Bi-directional, Open-drain, Active Low). This signal indicates a SCSI bus Reset condition. /SEL Select (Bi-directional, Open-drain, Active Low). This signal is used by an Initiator to select a Target, or by a Target to reselect an Initiator.
SCSI Bus
The following signals are all bi-directional, active Low, open-drain, with 48 mA sink capability. All pins interface directly with the SCSI bus. /ACK Acknowledge (Bi-directional, Open-drain, Active Low). Driven by an Initiator, /ACK indicates an acknowledgment for a /REQ//ACK data-transfer handshake. In the Target role, /ACK is received as a response to the /REQ signal. /ATN Attention (Bi-directional, Open-drain, Active Low). Driven by an Initiator, received by the Target, /ATN indicates an Attention condition. /BSY Busy (Bi-directional, Open-drain, Active Low). This signal indicates that the SCSI bus is being used and can be driven by both the Initiator and the Target device. C//D Control/Data (Bi-directional, Open-drain). Driven by the Target and received by the Initiator, C//D indicates whether Control or Data information is on the Data Bus. True indicates Control.
FUNCTIONAL DESCRIPTION
The Z5380 Small Computer System Interface (SCSI) has a set of eight registers that are controlled by the CPU. By reading and writing the appropriate registers, the CPU may initiate any SCSI Bus activity or may sample and assert any signal on the SCSI Bus. This allows the user to implement all or any of the SCSI protocol in software. These registers are read (written) by activating /CS with an address on A2-A0 and then issuing an /IOR (/IOW) pulse. This section describes the operation of the internal registers (Table 1).
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ZILOG Table 1. Register Summary A2 0 0 0 0 0 1 1 1 1 1 1 1 1 Address A1 A0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 1 1 R/W R W R/W R/W R/W R W R W R W R W Register Name Current SCSI Data Output Data Initiator Command Mode Target Command Current SCSI Bus Status Select Enable Bus and Status Start DMA Send Input Data Start DMA Target Receive Reset Parity/Interrupt Start DMA Initiator Receive
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Address: 0 (Read Only)
Z5380 SCSI
D7 D6 D5 D4 D3 D2 D1 D0
Figure 4. Current SCSI Data Register
Address: 0
(Write Only)
Data Registers
The data registers are used to transfer SCSI commands, data, status, and message bytes between the microprocessor Data Bus and the SCSI Bus. The Z5380 does not interpret any information that passes through the data registers. The data registers consist of the transparent Current SCSI Data Register, the Output Data Register, and the Input Data Register. Current SCSI Data Register. Address 0 (Read Only). The Current SCSI Data Register (Figure 4) is a read-only register which allows the microprocessor to read the active SCSI Data Bus. This is accomplished by activating /CS with an address on A2-A0 of 000 and issuing an /IOR pulse. If parity checking is enabled, the SCSI Bus parity is checked at the beginning of the read cycle. This register is used during a programmed I/O data read or during Arbitration to check for higher priority arbitrating devices. Parity is not guaranteed valid during Arbitration. Output Data Register. Address 0 (Write Only). The Output Data Register (Figure 5) is a write-only register that is used to send data to the SCSI Bus. This is accomplished by either using a normal CPU write, or under DMA control, by using /IOW and /DACK. This register also asserts the proper ID bits on the SCSI Bus during the Arbitration and Selection phases.
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
Figure 5. Output Data Register
Initiator Command Register. Address 1 (Read/Write). The Initiator Command Register (Figures 6 and 7) are read and write registers which assert certain SCSI Bus signals, monitors those signals, and monitors the progress of bus arbitration. Many of these bits are significant only when being used as an Initiator; however, most can be used during Target role operation.
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Z5380 SCSI This bit should also be set during DMA send operations. Bit 1. Assert /ATN. /ATN may be asserted on the SCSI Bus by setting this bit to a one (1) if the Target Mode bit (Mode Register, bit 6) is False. /ATN is normally asserted by the initiator to request a Message Out bus phase. Note that since Assert /SEL and Assert /ATN are in the same register, a select with /ATN may be implemented with one CPU write. /ATN may be deasserted by resetting this bit to zero. A read of this register simply reflects the status of this bit. Bit 2. Assert /SEL. Writing a one (1) into this bit position asserts /SEL onto the SCSI Bus. /SEL is normally asserted after Arbitration has been successfully completed. /SEL may be disabled by resetting bit 2 to a zero. A read of this register reflects the status of this bit. Bit 3. Assert /BSY. Writing a one (1) into this bit position asserts /BSY onto the SCSI Bus. Conversely, a zero resets the /BSY signal. Asserting /BSY indicates a successful selection or reselection. Resetting this bit creates a BusDisconnect condition. Reading this register reflects bit status. Bit 4. Assert /ACK. Bit 4 is used by the bus initiator to assert /ACK on the SCSI Bus. In order to assert /ACK, the Target Mode bit (Mode Register, bit 6) must be False. Writing a zero to this bit deasserts /ACK. Reading this register reflects bit status. Bit 5. "0" (Write Bit). Bit 5 should be written with a zero for proper operation. Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active, indicates that the SCSI detected a Bus-Free condition, arbitrated for use of the bus by asserting /BSY and its ID on the Data Bus, and lost Arbitration due to /SEL being asserted by another bus device. This bit is active only when the Arbitrate bit (Mode Register, bit 0) is active. Bit 6. Test Mode (Write Bit). Bit 6 is written during a test environment to disable all output drivers, effectively removing the Z5380 from the circuit. Resetting this bit returns the part to normal operation. Bit 6. AIP (Arbitration in Process - Read Bit). Bit 6 is used to determine if Arbitration is in progress. For this bit to be active, the Arbitrate bit (Mode Register, bit 0) must have been set previously. It indicates that a Bus-Free condition has been detected and that the chip has asserted /BSY and put the contents of the Output Data Register onto the SCSI Bus. AIP will remain active until the Arbitrate bit is reset. Bit 7. Assert /RST. Whenever a one is written to bit 7 of the Initiator Command Register, the /RST signal is asserted on
FUNCTIONAL DESCRIPTION (Continued)
Address: 1 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus Assert /ATN Assert /SEL Assert /BSY Assert /ACK Lost Arbitration Arbitration in Progress Assert /RST
Figure 6. Initiator Command Register
Address: 1
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus Assert /ATN Assert /SEL Assert /BSY Assert /ACK "0" Test Mode Assert /RST
Figure 7. Initiator Command Register
The following describes the operation of all bits in the Initiator Command Register: Bit 0. Assert Data Bus. This bit, when set, allows the contents of the Output Data Register to be enabled as chip outputs on the signals /DB7-DB0. Parity is also generated and asserted on /DBP. When connected as an Initiator, the outputs are only enabled if the Target Mode bit (Mode Register, bit 6) is 0, the received signal I//O is False, and the phase signals (C/ /D, I//O, and /MSG) match the contents of the Assert C//D, Assert I//O, and Assert /MSG in the Target Command Register.
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ZILOG the SCSI Bus. The /RST signal will remain asserted until this bit is reset or until an external /RESET occurs. After this bit is set (1), IRQ goes active and all internal logic and control registers are reset (except for the interrupt latch and the Assert /RST bit). Writing a zero to bit 7 of the Initiator Command Register deasserts the /RST signal. The status of this bit is monitored by reading the Initiator Command Register. Mode Register. Address 2 (Read/Write). The Mode Register controls the operation of the chip. This register determines whether the Z5380 operates as an Initiator or a Target, whether DMA transfers are being used, whether parity is checked, and whether interrupts are generated on various external conditions. This register is read to check the value of these internal control bits (Figure 8).
Address: 2 (Read/Write)
Z5380 SCSI Receive Register and set (0) for Start DMA Initiator Receive Register. The control bit Assert Data Bus (Initiator Command Register, bit 0) must be True (1) for all DMA send operations. In the DMA mode, /REQ and /ACK are automatically controlled. The DMA Mode bit is not reset upon the receipt of an /EOP signal. Any DMA transfer is stopped by writing a zero into this bit location; however, care must be taken not to cause /CS and /DACK to be active simultaneously. Bit 2. Monitor Busy. The Monitor Busy bit, when True (1), causes an interrupt to be generated for an unexpected loss of /BSY. When the interrupt is generated due to loss of /BSY, the lower six bits of the Initiator Command Register are reset (0) and all signals are removed from the SCSI Bus. Bit 3. Enable /EOP interrupt. The enable /EOP interrupt bit, when set (1), causes an interrupt to occur when the /EOP (End Of Process) signal is received from the DMA controller logic. Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt bit, when set (1), will cause an interrupt (IRQ) to occur if a parity error is detected. A parity interrupt will only be generated if the Enable Parity Checking bit (bit 5) is also enabled (1). Bit 5. Enable Parity Checking. The Enable Parity Checking bit determines whether parity errors are ignored or saved in the parity error latch. If this bit is reset (0), parity is ignored. Conversely, if this bit is set (1), parity errors are saved. Bit 6. Target Mode. The Target Mode bit allows the Z5380 to operate as a SCSI Bus Initiator or Target. With this bit reset (0), the Z5380 operates as a SCSI Bus Initiator. Setting Target Mode bit to 1 programs the Z5380 to operate as a SCSI Bus Target device. If the signals /ATN and /ACK are to be asserted on the SCSI Bus, the Target Mode bit must be reset (0). If the signals C//D, I//O, /MSG, and /REQ are to be asserted on the SCSI Bus, the Target Mode bit must be set (1). Bit 7. Block Mode DMA. The Block Mode DMA bit controls the characteristics of the DMA DRQ-/DACK handshake. When this bit is reset (0) and the DMA Mode bit is active (1), the DMA handshake uses the normal interlocked handshake, and the rising edge of /DACK indicates the end of each byte being transferred. In Block Mode operation, when the Block Mode DMA bit is set (1) and DMA Mode bit is active (1), the end of /IOR or /IOW signifies the end of each byte transferred and /DACK is allowed to remain active throughout the DMA operation. Ready can then be used to request the next transfer.
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate DMA Mode Monitor /BSY Enable /EOP Interrupt Enable Parity Interrupt Enable Parity Checking Target Mode Block Mode DMA
Figure 8. Mode Register
The following describes the operation of all bits in the Initiator Command Register: Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the Arbitration process. Prior to setting this bit, the Output Data Register should contain the proper SCSI device ID value. Only one data bit should be active for SCSI Bus Arbitration. The Z5380 waits for a Bus-Free condition before entering the Arbitration phase. The results of the Arbitration phase is determined by reading the status bits LA and AIP (Initiator Command Register, bits 5 and 6, respectively). Bit 1. DMA Mode. The DMA Mode bit is normally used to enable a DMA transfer and must be set (1) prior to writing Start DMA Send Register, Start DMA Target Register, and Start DMA Initiator Receiver Register. These three registers are used to start DMA transfers. The Target Mode bit (Mode Register, bit 6) must be consistent with writes to Start DMA Target Receive and Start DMA Initiator Receive Registers; i.e., set (1) for a write to Start DMA Target
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Z5380 SCSI
FUNCTIONAL DESCRIPTION (Continued)
Target Command Register. Address 3 (Read/Write). When connected as a target device, the Target Command Register (Figure 9) allows the CPU to control the SCSI Bus Information Transfer phase and/or to assert /REQ by writing this register. The Target Mode bit (Mode Register, bit 6) must be True (1) for bus assertion to occur. The SCSI Bus phases are described in Table 2.
Address: 3 (Read/Write)
/DBP /SEL
Initiator device can use this register to determine the current bus phase and to poll /REQ for pending data transfers. This register may also be used to determine why a particular interrupt occurred. Figure 10 describes the Current SCSI Bus Status Register.
Address: 4 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O Assert C//D Assert /MSG Assert /REQ "X"
I//O C//D /MSG /REQ /BSY /RST
Figure 9. Target Command Register Figure 10. Current SCSI Bus Status Register Table 2. SCSI Information Transfer Phases Bus Phase Data Out Unspecified Command Message Out Data In Unspecified Status Message In Assert I//O 0 0 0 0 1 1 1 1 Assert C//D 0 0 1 1 0 0 1 1 Assert /MSG 0 1 0 1 0 1 0 1 Select Enable Register. Address 4 (Write Only). The Select Enable Register (Figure 11) is a write-only register which is used as a mask to monitor a signal ID during a selection attempt. The simultaneous occurrence of the correct ID bit, /BSY False, and /SEL True causes an interrupt. This interrupt can be disabled by resetting all bits in this register. If the Enable Parity Checking bit (Mode Register, bit 5) is active (1), parity is checked during selection.
Address: 4 (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
When connected as an Initiator with DMA Mode bit True, if the phase lines (I//O, C//D, and /MSG) do not match the phase bits in the Target Command Register, a phase mismatch interrupt is generated when /REQ goes active. To send data as an Initiator, the Assert I//O, Assert C//D, and Assert /MSG bits must match the corresponding bits in the Current SCSI Bus Status Register. The Assert /REQ bit (bit 3) has no meaning when operating as an Initiator. Bits 4, 5, 6, and 7 are not used. Current SCSI Bus Status Register. Address 4 (Read Only). The Current SCSI Bus Register is a read-only register which is used to monitor seven SCSI Bus control signals, plus the Data Bus parity bit. For example, an
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
Figure 11. Select Enable Register
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ZILOG Bus and Status Register. Address 5 (Read Only). The Bus and Status Register (Figure 12) is a read-only register which can be used to monitor the remaining SCSI control signals not found in the Current SCSI Bus Status Registers (/ATN and /ACK), as well as six other status bits. The following describes each bit of the Bus and Status Register individually.
Address: 5 (Read Only)
Z5380 SCSI Bit 5. Parity Error. Bit 5 is set if a parity error occurs during a data receive or a device selection. The Parity Error bit can only be set (1) if the Enable Parity Check bit (Mode Register, bit 5) is active (1). This bit may be cleared by reading the Reset Parity/Interrupt Register. Bit 6. DMA Request. The DMA Request bit allows the CPU to sample the output pin DRQ. DRQ can be cleared by asserting /DACK or by resetting the DMA Mode bit (bit 1) in the Mode Register. The DRQ signal does not reset when a phase-mismatch interrupt occurs. Bit 7. End of DMA Transfer. The End of DMA Transfer bit is set if /EOP, /DACK, and either /IOR or /IOW are simultaneously active for at least 100 ns. Since the /EOP signal can occur during the last byte sent to the Output Data Register, the /REQ and /ACK signals should be monitored to ensure that the last byte has been transferred. This bit is reset when the DMA Mode bit is reset (0) in the Mode Register. Input Data Register. Address 6 (Read Only). The input Data Register (Figure 13) is a read-only register that is used to read latched data from the SCSI Bus. Data is latched either during a DMA Target receive operation when /ACK goes active or during a DMA Initiator receive when /REQ goes active. The DMA Mode bit (bit 1) must be set before data can be latched in the Input Data Register. This register is read under DMA control using /IOR and /DACK. Parity is optionally checked when the Input Data Register is loaded.
Address: 6 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA
Figure 12. Bus and Status Register
Bit 0. /ACK. Bit 0 reflects the condition of the SCSI Bus control signal /ACK. This signal is normally monitored by the Target device. Bit 1. /ATN. Bit 1 reflects the condition of the SCSI Bus control signal /ATN. This signal is normally monitored by the Target device. Bit 2. Busy Error. The Busy Error bit is active if an unexpected loss of the /BSY signal has occurred. This latch is set whenever the Monitor Busy bit (Mode Register, bit 2) is True and /BSY is False. An unexpected loss of /BSY disables any SCSI outputs and resets the DMA Mode bit (Mode Register, bit 1). Bit 3. Phase Match. The SCSI signals /MSG, C//D, and I//O, represent the current information Transfer phase. The Phase Match bit indicates whether the current SCSI Bus phase matches the lower 3 bits of the Target Command Register. Phase Match is continuously updated and is only significant when operating as a Bus Initiator. A phase match is required for data transfers to occur on the SCSI Bus. Bit 4.Interrupt Request ACTIVE. Bit 4 is set if an enabled interrupt condition occurs. It reflects the current state of the IRQ output and can be cleared by reading the Reset Parity/ Interrupt Register.
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
Figure 13. Input Data Register
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Z5380 SCSI
FUNCTIONAL DESCRIPTION (Continued) DMA Registers
Three write-only registers are used to initiate all DMA activity. They are: Start DMA Send, Start DMA Target Receive, and Start DMA Initiator Receive. Performing a write operation into one of these registers starts the desired type of DMA transfer. Data presented to the Z5380 on signals D7-D0 during the register write is meaningless and has no effect on the operation. Prior to writing these registers, the Block Mode DMA bit (bit 7), the DMA Mode bit (bit 1), and the Target Mode bit (bit 6) in the Mode Register must be appropriately set. The individual registers are briefly described as follows: Start DMA Send. Address 5 (Write Only). This register is written to initiate a DMA send, from the DMA to the SCSI Bus, for either Initiator or Target role operations. The DMA Mode bit (Mode Register, bit 1) is set prior to writing this register. Start DMA Target Receive. Address 6 (Write Only). This register is written to initiate a DMA receive - from the SCSI Bus to the DMA, for Target operation only. The DMA Mode bit (bit 1) and the Target Mode bit (bit 6) in the Mode Register must both be set (1) prior to writing this register. Start DMA Initiator Receive. Address 7 (Write Only). This register is written to initiate a DMA receive - from the SCSI Bus to the DMA, for Initiator operation only. The DMA Mode bit (bit 6) must be False (0) in the Mode Register prior to writing this register. Reset Parity/Interrupt. Address 7 (Read Only). Reading this register resets the Parity Error bit (bit 5), the Interrupt Request bit (bit 4), and the Busy Error bit (bit 2) in the Bus and Status Register. On-Chip SCSI Hardware Support The Z5380 is easy to use because of its simple architecture. The chip allows direct control and monitoring of the SCSI Bus by providing a latch for each signal. However, portions of the protocol define timings which are much too quick for traditional microprocessors to control. Therefore, hardware support has been provided for DMA transfers, bus arbitration, phase change monitoring, bus disconnection, bus reset, parity generation, parity checking, and device selection/reselection. Arbitration is accomplished using a bus-free filter to continuously monitor /BSY. If /BSY remains inactive for at least 1.2 s, the SCSI Bus is considered free and Arbitration may begin. Arbitration will begin if the bus is free, /SEL is inactive, and the Arbitrate bit (Mode Register, bit 0) is active. Once arbitration has begun (/BSY asserted), an arbitration delay of 2.2 s must elapse before the Data Bus can be examined to determine if Arbitration is enabled. This delay is implemented in the controlling software driver. The Z5380 is a clockwise device. Delays such as bus-free delay, bus-set delay, and bus-settle delay are implemented using gate delays. These delays may differ between devices because of inherent process variations, but are well within the proposed ANSI X3.131 - 1986 specification.
Interrupts
The Z5380 provides an interrupt output (IRQ) to indicate a task completion or an abnormal bus occurrence. The use of interrupts is optional and may be disabled by resetting the appropriate bits in the Mode Register or the Select Enable Register. When an interrupt occurs, the Bus and Status Register and the Current SCSI Bus Status Register (Figures 12 and 10) must be read to determine which condition created the interrupt. IRQ can be reset simply by reading the Reset Parity/Interrupt Register or by an external chip reset /RESET active for 200 ns. Assuming the Z5380 has been properly initialized, an interrupt is generated if the chip is selected or reselected; if an /EOP signal occurs during a DMA transfer; if a SCSI Bus reset occurs; if a parity error occurs during a data transfer; if a bus phase mismatch occurs; or if a SCSI Bus disconnection occurs. Selection/Reselection Interrupt The Z5380 generates a select interrupt if /SEL is active (0), its device ID is True and /BSY is False for at least a bussettle delay. If I//O is active, this is considered a reselect interrupt. The correct ID bit is determined by a match in the Select Enable Register. Only a single bit match is required to generate an interrupt. This interrupt may be disabled by writing zeros into all bits of the Select Enable Register. If parity is supported, parity should be good during the selection phase. Therefore, if the Enable Parity bit (Mode Register, bit 5) is active, the Parity Error bit is checked to ensure that a proper selection has occurred. The Enable Parity Interrupt bit need not be set for this interrupt to be generated.
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ZILOG The proposed SCSI specification also requires that no more than two device ID's be active during the selection process. To ensure this, the Current SCSI Data Register is read. The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 14 and 15, respectively.
D7 0 0 0 1 X 0 X D0 0
Z5380 SCSI The proper values for the Bus and Status Register and the Current SCSI Bus Status Register for this interrupt are shown in Figures 16 and 17.
D7 1 0 0 1 0 0 0 D0 X
/ACK /ATN Busy Error Phase Match
/ACK
Interrupt Request Active
/ATN
Parity Error
Busy Error
DMA Request
Phase Match
End of DMA
Interrupt Request Active Parity Error DMA Request End of DMA
Figure 16. Bus and Status Register
Figure 14. Bus and Status Register
D7 0 1 1 X X X 0
D0 X
D7 0 0 0 X X X 0
D0 X
/DBP /SEL I//O
/DBP /SEL I//O C//D /MSG /REQ /BSY /RST
C//D /MSG /REQ /BSY /RST
Figure 17. Current SCSI Bus Status Register
Figure 15. Current SCSI Bus Status Register
End Of Process (EOP) Interrupt An End Of Process signal (EOP) which occurs during a DMA transfer (DMA Mode True) will set the End of DMA Status bit (bit 7) and will optionally generate an interrupt if Enable EOP Interrupt bit (Mode Register, bit 3) is True. The /EOP pulse will not be recognized (End of DMA bit set) unless /EOP, /DACK, and either /IOR or /IOW are concurrently active for at least 100 ns. DMA transfers can still occur if /EOP was not asserted at the correct time. This interrupt is disabled by resetting the Enable EOP Interrupt bit.
The End of DMA bit is used to determine when a block transfer is complete. Receive operations are complete when there is no data left in the chip and no additional handshakes occurring. The only exception to this is receiving data as an Initiator and the Target opts to send additional data for the same phase. In this /REQ goes active and the new data is present in the Input Data Register. Since a phase-mismatch interrupt will not occur, /REQ and /ACK need to be sampled to determine that the Target is attempting to send more data.
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FUNCTIONAL DESCRIPTION (Continued)
D7 D0 X X X X X X X
For send operations, the End of DMA bit is set when the DMA finishes its transfers, but the SCSI transfer may still be in progress. If connected as a Target, /REQ and /ACK should be sampled until both are False. If connected as an Initiator, a phase change interrupt is used to signal the completion of the previous phase. It is possible for the Target to request additional data for the same phase. In this case, a phase change will not occur and both /REQ and /ACK are sampled to determine when the last byte was transferred. SCSI Bus Reset Interrupt The Z5380 generates an interrupt when the /RST signal transitions to True. The device releases all bus signals within a bus-clear delay of this transition. This interrupt also occurs after setting the Assert /RST bit (Initiator Command Register, bit 7). This interrupt cannot be disabled. (Note: /RST is not latched in bit 7 of the Current SCSI Bus Status Register and is not active when this port is read. For this case, the Bus Reset interrupt is determined by default.) The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 18 and 19, respectively.
D7 0 X 0 1 X 0 X D0 X
X
/DBP /SEL I//O C//D /MSG /REQ /BSY /RST
Figure 19. Current SCSI Bus Status Register
Parity Error Interrupt An Interrupt is generated for a received parity error if the Enable Parity Check (bit 5) and the Enable Parity Interrupt (bit 4) bits are set (1) in the Mode Register. Parity is checked during a read of the Current SCSI Data Register and during a DMA receive operation. A parity error can be detected without generating an interrupt by disabling the Enable Parity Interrupt bit and checking the Parity Error flag (Bus and Status Register, bit 5). The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 20 and 21, respectively.
D7 0 X 1 1 1 0 X D0 X
/ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA
/ACK /ATN Busy Error Phase Match
Figure 18. Bus and Status Register
Interrupt Request Active Parity Error DMA Request End of DMA
Figure 20. Bus and Status Register
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D7 0 1 1 X X X 0 D0 X
Z5380 SCSI
D7 0 0 0 1 0 0 X D0 0
/DBP /SEL I//O C//D /MSG /REQ /BSY /RST
/ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA
Figure 21. Current SCSI Bus Status Register
D7 0 1
Figure 22. Bus and Status Register
D0 X X X X 0 X
Bus Phase Mismatch Interrupt The SCSI phase lines are comprised of the signals I//O, C//D, and /MSG. These signals are compared with the corresponding bits in the Target Command Register: Assert I//O (bit 0), Assert C//D (bit 1), and Assert /MSG (bit 2). The comparison occurs continually and is reflected in the Phase Match bit (bit 3) of the Bus and Status Register. If the DMA Mode bit (Mode Register, bit 1) is active and a phase mismatch occurs when /REQ transitions from False to True, an interrupt (IRQ) is generated. A phase mismatch prevents the recognition of /REQ and removes the chip from the bus during an Initiator send operation (/DB7-/DB0 and /DBP will not be driven even through the Assert Data Bus bit (Initiator Command Register, bit 0) is active). This may be disabled by resetting the DMA Mode bit (Note: It is possible for this interrupt to occur when connected as a Target if another device is driving the phase lines to a different state). The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 22 and 23, respectively.
/DBP /SEL I//O C//D /MSG /REQ /BSY /RST
Figure 23. Current SCSI Bus Status Register
Loss of BSY Interrupt If the Monitor Busy bit (bit 2) in the Mode Register is active, an interrupt is generated if the BSY signal goes False for at least a bus-settle delay. This interrupt is disabled by resetting the Monitor Busy bit. Register values are displayed in Figures 24 and 25.
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FUNCTIONAL DESCRIPTION (Continued)
D7 0 0 0 1 X 1 0 D0 0
reading the Current SCSI Bus Status Register; however, this signal is not latched and may not be present when this port is read).
/ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA
SCSI Bus Reset (/RST) Issued If the CPU sets the Assert /RST bit (bit 7) in the Initiator Command Register, the /RST signal goes active on the SCSI Bus and an internal reset is performed. Again, all internal logic and registers are cleared except for the IRQ interrupt latch and the Assert /RST bit (bit 7) in the Initiator Command Register. The /RST signal will continue to be active until the Assert /RST bit is reset or until a hardware reset occurs. Data Transfers Data is transferred between SCSI Bus devices in one of four modes (Reference Figures 26-41): 1. 2. 3. 4. Programmed I/O Normal DMA Block Mode DMA Pseudo DMA
Figure 24. Bus and Status Register
D7 0 0 0 X X X 0 D0 0
/DBP /SEL I//O C//D /MSG /REQ /BSY /RST
The following sections describe these modes in detail (Note: For all data transfer operations, /DACK and /CS should never be active simultaneously). Programmed I/O Transfers Programmed I/O is the most primitive form of data transfer. The /REQ and /ACK handshake signals are individually monitored and asserted by reading and writing the appropriate register bits. This type of transfer is normally used when transferring small blocks of data such as command blocks or message and status bytes. An Initiator send operation would begin by setting the C//D, I//O, and /MSG bits in the Target Command Register to the correct state so that a phase match exists. In addition to the phase match condition, it is necessary for the Assert Data Bus bit (Initiator Command Register, bit 0) to be True and the received I/O signal to be False for the Z5380 to send data. For each transfer, the data is loaded into the Output Data Register. The CPU then waits for the /REQ bit (Current SCSI Bus Status Register, bit 5) to become active. Once /REQ goes active, the Phase Match bit (Bus and Status Register, bit 3) is checked and the Assert /ACK bit (Initiator Command Register, bit 4) is set. The /REQ bit is sampled until it becomes False and the CPU resets the Assert /ACK bit to complete the transfer. Normal DMA Mode DMA transfers are normally used for large block transfers. The SCSI chip outputs a DMA request (DRQ) whenever it is ready for a byte transfer. External DMA logic uses this
Figure 25. Current SCSI Bus Status Register
Reset Conditions Three possible reset situations exist with the Z5380, as follows: Hardware Chip Reset When the signal /RST is active for at least 200 ns, the Z5380 device is re-initialized and all internal logic and control registers are cleared. This is a chip reset only and does not create a SCSI Bus-Reset condition. SCSI Bus Reset (/RST) Received When a SCSI /RST signal is received, an IRQ interrupt is generated and a chip reset is performed. All internal logic and registers are cleared, except for the IRQ interrupt latch and the Assert /RST bit (bit 7) in the Initiator Command Register. (Note: The /RST signal may be sampled by
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ZILOG DRQ signal to generate /DACK and an /IOR or an /IOW pulse to the Z5380. DRQ goes inactive when /DACK is asserted and /DACK goes inactive some time after the minimum read or write pulse width. This process is repeated for every byte. For this mode, /DACK should not be allowed to cycle unless a transfer is taking place. Block Mode DMA Some popular DMA Controllers, such as the 9517A, provide a Block Mode DMA transfer. This type of transfer allows the DMA controller to transfer blocks of data without relinquishing the use of the Data Bus to the CPU after each byte is transferred; thus, faster transfer rates are achieved by eliminating the repetitive access and release of the CPU Bus. If the Block Mode DMA bit (Mode Register, bit 7) is active, the Z5380 begins the transfer by asserting DRQ. The DMA controller then asserts /DACK for the remainder of the block transfer. DRQ goes inactive for the duration of the transfer. The Ready output is used to control the transfer rate. Non-Block Mode DMA transfers end when /DACK goes False, whereas Block Mode DMA transfers end when /IOR or /IOW becomes inactive. Since this is the case, DMA transfers may be started sooner in a Block Mode transfer. To obtain optimum performance in Block Mode operation, the DMA logic optionally uses the normal DMA mode interlocking handshake. Ready is still available to throttle the DMA transfer, but DRQ is 30 to 40 ns faster than Ready and is used to start the cycle sooner. The methods described under "Halting a DMA Operation" apply for all DMA operations. Pseudo DMA Mode To avoid the tedium of monitoring and asserting the request/acknowledgment handshake signals for programmed I/O transfers, the system can be designed to implement a pseudo DMA mode. This mode is implemented by programming the Z5380 to operate in the DMA mode, but using the CPU to emulate the DMA handshake. DRQ may be detected by polling the DMA Request bit (bit 6) in the Bus and Status Register, by sampling the signal through an external port, or by using it to generate a CPU interrupt. Once DRQ is detected, the CPU can perform a read or write data transfer. This CPU read/write is externally decoded to generate the appropriate /DACK and /IOR or /IOW signals. Often, external decoding logic is necessary to generate the Z5380 /CS signal. This same logic may be used to generate /DACK at no extra cost and provide an increased performance in programmed I/O transfers.
Z5380 SCSI Halting a DMA Operation The /EOP signal is not the only way to halt a DMA transfer. A bus phase mismatch or a reset of the DMA Mode bit (Mode Register, bit 1) can also terminate a DMA cycle for the current bus phase. Using the /EOP Signal If /EOP is used, it should be asserted for at least 100 ns while /DACK and /IOR or /IOW are simultaneously active. Note, however, that if /IOR or /IOW is not active, an interrupt is generated, but the DMA activity continues. The /EOP signal does not reset the DMA Mode bit. Since the /EOP signal can occur during the last byte sent to the Output Data Register, the /REQ and /ACK signals are monitored to ensure that the last byte has transferred. Bus Phase Mismatch Interrupt A bus phase mismatch interrupt is used to halt the transfer if operating as an Initiator. Using this method frees the host from maintaining a data length counter and frees the DMA logic from providing the /EOP signal. If performing an Initiator send operation, the Z5380 requires /DACK to cycle before /ACK goes inactive. Since phase changes cannot occur if /ACK is active, either /DACK must be cycled after the last byte is sent or the DMA Mode bit must be reset in order to receive the phase mismatch interrupt. Resetting the DMA Mode Bit A DMA operation may be halted at any time simply by resetting the DMA Mode bit. It is recommended that the DMA Mode bit be reset after receiving an /EOP or bus phase-mismatch interrupt. The DMA Mode bit must then be set before writing any of the start DMA registers for subsequent bus phases. If resetting the DMA Mode bit is used instead of /EOP for Target role operation, then care must be taken to reset this bit at the proper time. If receiving data as a Target device, the DMA Mode bit must be reset once the last DRQ is received and before /DACK is asserted to prevent an additional /REQ from occurring. Resetting this bit causes DRQ to go inactive. However, the last byte received remains in the Input Data Register and may be obtained either by performing a normal CPU read or by cycling /DACK and /IOR. In most cases, /EOP is easier to use when operating as a Target device.
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READ REGISTERS
Address: 0 (Read Only)
Address: 3
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
Address: 4 (Read Only)
Assert I//O Assert C//D Assert /MSG Assert /REQ "0"
Figure 29. Target Command Register
Figure 26. Current SCSI Data Register
Address: 1 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DBP /SEL I//O
Assert Data Bus Assert /ATN Assert /SEL Assert /BSY Assert /ACK Lost Arbitration Arbitration in Progress Assert /RST
D7 D6 D5 D4 D3 D2 D1 D0
C//D /MSG /REQ /BSY /RST
Figure 30. Current SCSI Bus Status Register
Address: 5
(Read Only)
Figure 27. Initiator Command Register
Address: 2 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/ACK /ATN Busy Error
Arbitrate DMA Mode Monitor /BSY Enable /EOP Interrupt Enable Parity Interrupt Enable Parity Checking Target Mode Block Mode DMA
D7 D6 D5 D4 D3 D2 D1 D0
Phase Match Interrupt Request Active Parity Error DMA Request End of DMA
Figure 31. Bus and Status Register
Figure 28. Mode Register
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Address: 6 (Read Only)
Z5380 SCSI
Address: 7 (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
"X" X = Don't Care
Figure 33. Reset Parity/Interrupt
Figure 32. Input Data Register
WRITE REGISTERS
Address: 0 (Write Only)
Address: 2 (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7
Arbitrate DMA Mode Monitor /BSY Enable /EOP Interrupt Enable Parity Interrupt Enable Parity Checking Target Mode Block Mode DMA
Figure 34. Output Data Register
Figure 36. Mode Register
Address: 1
(Write Only)
Address: 3
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus Assert /ATN Assert /SEL Assert /BSY Assert /ACK "0" Test Mode Assert /RST
Assert I//O Assert C//D Assert /MSG Assert /REQ "X"
Figure 37. Target Command Register
Figure 35. Initiator Command Register
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WRITE REGISTERS (Continued)
Address: 4 (Write Only)
Address: 6
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
/DB0 /DB1 /DB2 /DB3 /DB4 /DB5
"X"
Figure 40. Start DMA Target Receive
Address: 7
/DB6 /DB7
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
"X"
Figure 38. Select Enable Register Figure 41. Start DMA Initiator Receive
Address: 5 (Write Only) D7 D6 D5 D4 D3 D2 D1 D0
"X"
Figure 39. Start DMA Send
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect to GND ................................. -0.3V to +7.0V Operating Ambient Temperature ................................... Storage Temperature ............................ -65C to +150C
Note: See Ordering Information
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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STANDARD TEST CONDITIONS
The DC Characteristics section below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard conditions are as follows (Figures 42 and 43):
s s s
VL
2K
+4.5V < VCC < +5.5V GND = 0V TA as specified in Ordering Information
2.0 Test Points 0.4 0.8 0.8 2.0
From Output Under Test
120 pf
9K
2.4
Figure 42. Switching Test Circuit
Figure 43. Standard Test Load
DC CHARACTERISTICS Z5380
Symbol VDD VIH VIL IIH1 IIH2 IIL1 IIL2 VOH VOL1 VOL2 IDD TA Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Input Current SCSI Bus Pins High-Level Input Current All Other Pins Low-Level Input Current SCSI Bus Pins Low-Level Input Current All Other Pins High-Level Output Voltage Low-Level Output Voltage SCSI Bus Pins Low-Level Output Voltage All Other Pins Supply Current Operating Free-Air VIH = 5.25V VIL = 0V VIH = 5.25V VIL = 0V VIH = 5.25V VIL = 0V VIH = 5.25V VIL = 0V IOH = -3 mA VDD = 4.75V IOL = 48 mA VDD = 4.75V IOL = 7 mA VDD = 4.75V 15 mA -50 -10 2.4 0.5 0.5 Conditions Min 4.75 2.0 -0.3 Max 5.25 5.25 0.8 50 10 Units V V V A A A A V V V
0
70
C
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AC CHARACTERISTICS CPU Write Cycle Timing Diagram
A2-A0
1 2
/CS
3 4
/IOW
5 6
D7-D0
Figure 44. CPU Write Cycle
AC CHARACTERISTICS CPU Write Cycle Timing Table
No 1 2 3 4 5 6 Description Address Setup to Write Enable [1] Address Hold from End Write Enable [1] Write Enable Width [1] Chip Select Hold from End of /IOW Data Setup to end of Write Enable [1] Data Hold Time form End of /IOW Min 20 20 70 0 50 30 Max Units ns ns ns ns ns ns
Note: [1] Write Enable is the occurrence of /IOW and /CS.
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AC CHARACTERISTICS CPU Read Cycle Timing Diagram
A2-A0
1 2
/CS
3
/IOR
4 5
D7-D0
Figure 45. CPU Read Cycle
AC CHARACTERISTICS CPU Read Cycle Timing Table
No 1 2 3 4 5 Description Address Setup to Read Enable [1] Address Hold from End Read Enable [1] Chip Select Hold from End of /IOR Data Access Time from Read Enable [1] Data Hold Time from End of Read Enable [1] Min 20 20 0 130 20 Max Units ns ns ns ns ns
Note: [1] Read Enable is the occurrence of /IOR and /CS.
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AC CHARACTERISTICS DMA Write (Non-Block Mode) Target Send Cycle Timing Diagram
DRQ
1 2
/DACK
3 4
/IOW
5 6
D7-D0
7
/EOP
8 9
/REQ
11
10
/ACK
12 13
/DB7-/DB0, /DBP
Figure 46. DMA Write (Non-Block Mode) Target Send Cycle
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AC CHARACTERISTICS DMA Write (Non-Block Mode) Target Send Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 13 Description DRQ Low from /DACK Low /DACK High to DRQ High Write Enable Width [1] /DACK Hold from /IOW High Data Setup to End of Write Enable [1] Data Hold Time from End of /IOW Width of /EOP Pulse [2] /ACK Low to /REQ High /REQ from End of /DACK (/ACK High) /ACK Low to DRQ High (Target) /ACK High to /REQ Low (/DACK High) Data Hold from Write Enable Data Setup to /REQ Low (Target) Min 130 30 100 0 50 40 100 25 30 15 20 15 60 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
125 150 110 150
Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS DMA Write (Non-Block Mode) Initiator Send Cycle Timing Diagram
DRQ
1 2
/DACK
3 4
/IOW
5 6
D7-D0
7
/EOP
/REQ
8 9 10
/ACK
12 11
/DB7-/DB0, /DBP
Figure 47. DMA Write (Non-Block Mode) Initiator Send Cycle
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AC CHARACTERISTICS DMA Write (Non-Block Mode) Initiator Send Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 Description DRQ Low from /DACK Low /DACK High to DRQ High Write Enable Width [1] /DACK Hold from End of /IOW Data Setup to End of Write Enable [1] Data Hold Time from End of /IOW Width of /EOP Pulse [2] /REQ Low to /ACK Low /REQ High to DRQ High /DACK High to /ACK High /IOW High to Valid SCSI Data Data Hold from Write Enable [1] Min 130 30 100 0 50 40 100 20 20 25 100 15 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
160 110 150
Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS DMA Read (Non-Block Mode) Target Receive Cycle Timing Diagram
DRQ
1 2
/DACK
3
/IOR
4 5
D7-D0
6
/EOP
7 8
/REQ
9 10
/ACK
11 12
/DB7-/DB0, /DBP
Figure 48. DMA Read (Non-Block Mode) Target Receive Cycle
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AC CHARACTERISTICS DMA Read (Non-Block Mode) Target Receive Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 Description DRQ Low from /DACK Low /DACK High to DRQ High /DACK Hold Time from End of /IOR Data Access Time from Read Enable [1] Data Hold Time from End of /IOR Width of /EOP Pulse [2] /ACK Low to DRQ High /DACK High to /REQ Low (/ACK High) /ACK Low to /REQ High /ACK High to /REQ Low (/DACK High) Data Setup Time to /ACK Data Hold Time from /ACK Min 130 30 0 115 20 100 15 30 25 20 20 50 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
110 150 125 150
Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS DMA Read (Non-Block Mode) Initiator Receive Cycle Timing Diagram
DRQ
1 2
/DACK
3
/IOR
4 5
D7-D0
6
/EOP
7 8
/REQ
9 10
/ACK
11 12
/DB7-/DB0, /DBP
Figure 49. DMA Read (Non-Block Mode) Initiator Receive Cycle
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AC CHARACTERISTICS DMA Read (Non-Block Mode) Initiator Receive Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 Description DRQ Low from /DACK Low /DACK High to DRQ High /DACK Hold Time from End of /IOR Data Access Time from Read Enable [1] Data Hold Time from End of /IOR Width of /EOP Pulse [2] /REQ Low to DRQ High /DACK High to /ACK High (/REQ High) /REQ Low to /ACK Low /REQ High to /ACK High (/DACK High) Data Setup Time to /REQ Data Hold Time from /REQ Min 130 30 0 115 20 100 20 25 20 15 20 50 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
160 160 140
Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS DMA Write (Block Mode) Target Send Cycle Timing Diagram
DRQ
1
/DACK
2 3
/IOW
4 5
D7-D0
6
/EOP
7 8
/REQ
9
/ACK
10 11 12
READY
13 14
/DB7-/DB0, /DBP
Figure 50. DMA Write (Block Mode) Target Send Cycle
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AC CHARACTERISTICS DMA Write (Block Mode) Target Send Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description DRQ Low from /DACK Low Write Enable Width [1] Write Recovery Time Data Setup to End of Write Enable [1] Data Hold Time from End of /IOW Width of /EOP Pulse [2] /ACK Low to /REQ High /REQ from End of /IOW (/ACK High) /REQ from End of /ACK (/IOW High) /ACK Low to READY High READY High to /IOW High /IOW High to READY Low Data Hold from /ACK Low Data Setup to /REQ Low Min 130 100 120 50 40 100 25 40 20 20 70 20 40 60 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
125 180 170 140 140
Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS DMA Read (Block Mode) Target Receive Cycle Timing Diagram
DRQ
1
/DACK
2
/IOR
3 4
D7-D0
5
/EOP
6
/REQ
7 8
/ACK
9 10 11
READY
12 13
/DB7-/DB0, /DBP
Figure 51. DMA Read (Block Mode) Target Receive Cycle
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AC CHARACTERISTICS DMA Read (Block Mode) Target Receive Cycle Table
No 1 2 3 4 5 6 7 8 9 10 11 12 13 Description DRQ Low from /DACK Low /IOR Recovery Time Data Access Time from Read Enable [1] Data Hold Time from End of /IOR Width of /EOP Pulse [2] /IOR High to /REQ Low /ACK Low to /REQ High /ACK High to /REQ Low (/IOR High) /ACK Low to READY High READY High to Valid Data /IOR High to READY Low Data Setup Time to /ACK Data Hold Time from /ACK Min 130 120 110 20 100 30 25 20 20 50 20 20 50 190 125 170 140 140 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T5 for proper recognition of the /EOP pulse.
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AC CHARACTERISTICS Arbitration
/RST
/SEL
1
/BSY
2
/DB7-DB0, /DBP
ARBITRATE
Figure 52. Arbitration
No 1 2
Description Bus Clear from /SEL Low Arbitrate Start from /BSY High
Min 1200
Max 600 2200
Units ns ns
AC CHARACTERISTICS Reset
1
/RESET
Figure 53. Reset
No 1
Description Minimum Width of /RESET
Min 200
Max
Units ns
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Z5380 NOTES
1. Edge-triggered /RST Interrupt. If the SCSI Bus is not terminated, the /RST interrupt is continually generated. 2. True End of DMA Interrupt. The Z5380 generates an interrupt when it receives the last byte from the DMA, not when the last byte is transferred to the SCSI Bus. 3. Return to Ready after /EOP Interrupt. When operating in Block Mode DMA, the Z5380 does not return the Ready signal to a Ready condition. This locks up the bus and prevents the CPU from executing. 4. SCSI handshake after /EOP occurs. If an EOP occurs when receiving data, a subsequent request will cause /ACK to be asserted even though no DRQ is issued. 5. Reselection Interrupt. During reselection, if the Target Command Register does not reflect the current bus phase (most likely Data Out), the reselection interrupt may get reset. 6. Phase Mismatch Interrupt. A phase mismatch interrupt is not guaranteed after a reselection for the following reasons: - DMA Mode bit must be set in order to receive a phase mismatch interrupt. - DMA Mode bit can not be set unless /BSY is active. - /BSY can not be asserted until after the reselection has occurred. - Once /BSY is asserted, the Target may assert /REQ in less than 500 ns. - The phase mismatch interrupt is generated on the active edge of /REQ. If the DMA Mode bit is not set before the /REQ goes active, the phase mismatch interrupt will not occur.
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Z5380 SCSI
PACKAGE INFORMATION
40-Pin DIP Package Diagram
44-Pin PLCC Package Diagram
36
PS009101-0201
PS97SCC0100
ZILOG
Z5380 SCSI
ORDERING INFORMATION Z5380 SCSI
40-Pin DIP Z0538001PSC 44-Pin PLCC Z0538001VSC
Package
P = Plastic DIP V = Plastic Leadless Chip Carrier
Temperature
S = 0C to +70C E = -40C to +85C
Speed
1.5 MB/s
Environmental
C = Plastic Standard Example: Z 5380 01 V S
C
is a Z5380, 1.5 MB/s, PLCC, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
PS97SCC0100
PS009101-0201
37

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